V-11

The V-11, code-named "Scorpio", is a miniprocessor chip set implementation of the VAX instruction set architecture (ISA) developed and fabricated by Digital Equipment Corporation (DEC).

The V-11 was Digital's first VAX microprocessor design, but was the second to ship, after the MicroVAX 78032. It was presented at the 39th International Solid State Circuits Conference held in 1984 alongside the MicroVAX 78032 and was introduced in early 1986 in systems, operating at 5 MHz (200 ns cycle time) and in 1987 at 6.25 MHz (160 ns cycle time). The V-11 was proprietary to DEC and was only used in their VAX 8200, VAX 8250, VAX 8300 and VAX 8350 minicomputers; and the VAXstation 8000 workstation.

At 5 MHz, the V-11 performed approximately the same as the VAX-11/780 superminicomputer. At 6.25 MHz, it performed approximately 1.2 times faster than the VAX-11/780.

The V-11 was part of the Scorpio program, which aimed at providing DEC with the ability to develop and fabricate very-large-scale integration (VLSI) integrated circuits (ICs). Other aspects of the program were the development of a new computer-aided design (CAD) suite and semiconductor process, the results of which are CHAS and ZMOS, respectively. ZMOS was the first semiconductor process to be developed entirely by DEC.

The V-11 was a multichip design, mainly consisting of an I/E chip, a M chip, a F chip and five ROM/RAM chips. Unlike the MicroVAX 78032, which implemented a subset of VAX ISA, the V-11 was a complete VAX implementation, supporting all of the 304 instructions and 17 data types (byte, word, longword, quadword, octaword, F-floating, D-floating, G-floating, H-floating, bit, variable-length bit field, character string, trailing numeric string, leading separate numeric string, packed decimal string, absolute queue, and self-relative queue).

The chips in the chip set were connected with four buses: the MIB, DAL, PAL and CAL. The MIB (microinstruction bus) carried microinstructions control signals and addresses from the control store to the I/E and F chips. The MIB is 40 bits wide, the same width as a microword and is parity protected. The DAL is a 32-bit parity-protected bus that carries data addresses to and from the I/E, M and F chips, cache, backup translation buffer RAMs and the port interface.

This page was last edited on 30 October 2012, at 18:40 (UTC).
Reference: https://en.wikipedia.org/wiki/ZMOS under CC BY-SA license.

Related Topics

Recently Viewed